The present invention relates to a central processing unit and, more particularly, to a micro processor capable of being connected with a coprocessor.
In a micro processor fabricated on a single semiconductor chip, the number of circuit elements formed within the single chip is restricted, and hence it is difficult to fabricate a unit in the same chip that executes high level instructions such as a floating-point arithmetic operation, a function arithmetic operation, etc., at a high speed. In order to solve this problem, therefore, a coprocessor is employed, which executes the high level instructions in place of the micro processor. The coprocessor operates under the control of the micro processor and is thus called a "slave processor". The micro processor operates by itself as a central processing unit (CPU) to control the coprocessor along with a memory and peripheral units and is thus called a "master processor".
When the master processor decodes the high level instruction, it accesses the slave processor. If the master processor is not connected with the slave processor, the master processor should execute the high level instruction by use of its arithmetic unit. Therefore, the master processor requires means for detecting whether or not the slave processor is connected thereto.
For this purpose, a prior art system provides in the master processor a flag representative of the presence or absence of the slave processor. When the master processor decodes the high level instruction, it reads out and checks the content of the flag. When the flag is stored with information representative of the presence of the slave processor, the master processor accesses the slave processor to supply command information thereto. When the content of the flag represents that the slave processor is not provided, the master processor executes the instruction by itself. According to this prior art, however, the master processor should check the content of the flag irrespective of the presence of the slave processor. For this reason, the executing time of the high level instruction is prolonged which lowers the arithmetic speed. Moreover, in a case where a plurality of slave processors are required, a plurality of flags corresponding to the respective slave processors are necessitated which undesirably increases the hardware of the master processor.